Verification Academy

Harry Foster

Lead Subject Matter Expert

Evolving Capabilities | Assertion-Based Verification | Clock-Domain Crossing Verification

Web Seminar Recording: A Roadmap to Advanced Functional Verification Adoption (login required)

Harry Foster is Chief Verification Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored five books on verification--including the 2008 Springer book Creating Assertion-Based IP. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

Tom Fitzpatrick

Advanced OVM (&UVM - Universal Verification Methodology) Module

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group.

At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Ray Salemi

Evolving FPGA Verification Capabilities

Ray Salemi is a 20-year veteran of the EDA industry and is an expert in the use of RTL in design flows. He is the author of "FPGA Simulation: A Complete Step-by-Step Guide" and of "Leading After a Layoff: Reignite Your Team's Productivity Quickly"

Ray stared in EDA as the manager of customer support for Gateway Design Automation -- the founder of Verilog and then for Cadence Design Systems. As a CAE Manager for Sun Microsystems, Ray led teams that created Sun's ASIC development environments. Recently Ray has worked for Exemplar, and Mentor Graphics focusing on FPGA design, verification, and synthesis.

John Aynsley

Basic OVM (Open Verification Methodology) Module

John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specializing in simulation, languages (particularly VHDL, SystemVerilog, and SystemC), hardware verification and system modeling, and has written many training courses and technical papers in these areas. He is co-author of the IEEE 1666 SystemC standard, author of the OSCI TLM-2.0 LRM, and an active contributor to several technical working groups and forums. His current role spans technical consulting, technical marketing, and business management.

Chuck Seeley

ABV Module | Session 10 | Questa Simulation ABV Demo

Chuck Seeley has over 27 years of experience in engineering design and verification, and technical marketing. As a Technical Marketing Engineer at Mentor Graphics Corporation he specializes in both assertion-based verification and coverage driven verification methods. He holds a BSEE from Portland State University.

Mark Eslinger

ABV Module | Session 11 | Formal ABV Demo

Mark Eslinger has over 20 years of experience in chip design and verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics, Mr. Eslinger has a special focus on assertion-based methods and formal verification. He works with customers worldwide to help them adopt advanced methodologies.

Prior to Mentor Mr. Eslinger held positions in the engineering and technical marketing organizations in the semiconductor, systems, and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. He holds a MSEE from Santa Clara University.

Kurt Takara

CDC Module | Session 7 | Clock-Domain Crossing Demo

Kurt Takara has over 20 years of experience in engineering design and verification, technical marketing and engineering services. He is a Technical Marketing Engineer at Mentor Graphics Corporation and specializes in assertion-based verification methods and applications, including formal and clock-domain crossing (CDC) verification. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.